A semiconductor device such as an IC (integrated circuit) has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC circuit elements while increasing their number on a single body. Additional miniaturization is highly desirable for improved IC performance and cost reduction.
Consequently, the spacing between the metal lines on any given plane of an IC has become smaller and smaller, now extending into the submicrometer range. By reducing the spacing between conductive members in the IC, an increase in capacitive coupling occurs. This increase in capacitive coupling causes greater crosstalk, higher capacitive losses and increased RC time constant.
In order to reduce capacitive coupling, new developments and implementation of low dielectric constant (low-k) materials have been proposed to replace classic dielectric materials that are interposed between the metal lines on a given layer and between layers. Typically, conventional electronic insulators have dielectric constants in the 3.5 to 4.2 range. For example, silicon dioxide (SiO2) has a dielectric constant of 4.2, and advanced polymers have dielectric constants in the 2.5 to 3.0 range. Insulating materials having lower dielectric constants are known, but such materials have been associated with problems such as processing, cost and instability.
Therefore, in back-end-of-line (BEOL) processing, a very important change included the replacement of low-k dielectrics with ultralow-k dielectrics such as air gaps because air gaps have the lowest k value of any material (k value of about 1.0). The lowest possible dielectric constant is 1.0, which is the dielectric constant of a vacuum, and air has a dielectric constant of 1.001. Given this recognition of the low dielectric constant of air, attempts have been made to fabricate semiconductor devices with air gaps between metal leads to reduce the capacitive coupling between the electrically conducting members. The air gap forming techniques that have been used with varying degrees of complexity and limitations.
There are several techniques for forming air gaps or regions in a semiconductor device. Typically, integration schemes are known for forming air gaps using non-conformal CVD (Chemical Vapor Deposition). Notably, as illustrated in FIG. 1, for example, when air cavities are formed prior to the via etching process, if the via-misalignment is too wide, or the via etching is not stopped by a specific material (etching selectivity), prior to the formation of the cavity breakthrough, the cavities remain open (e.g., opening 1 shown in FIG. 1). Consequently, some metal material will be deposited inside the as-opened cavities during the next integration step which can be a serious issue with regards to interconnect reliability.
Further, referring to FIG. 2, to overcome via-misalignment issues during air-gap formation using non-conformal CVD processes, a conventional technique proposes to locally enlarge the line width 2 to guide the via landing. However, this solution is detrimental to the density and performance of the IC devices.
Moreover, to avoid via-misalignment issues, for instance, the use of an additional lithographic step has been proposed. This particular solution as illustrated in FIG. 3, however, leads to some dielectric liner 3 remaining on top of the interconnect stack at the metal level, thus reducing interconnect performance, although via misalignment can be lessened using this method. Another concern is that the trenches must be narrower than metal spice and the metal-to-metal misalignment must be taken into account. This problem makes this approach very expensive and complex as the lithographic step must be repeated at the creation of each metal level.
Therefore, in view of these concerns, there is a continuing need for developing a new and improved method in which integration of self-aligned trenches in-between metal lines can be carried out, which addresses the above mentioned problems. In particular, it is desirable to simultaneously ensure a larger via-landing to overcome via-misalignment issues without degrading the intra-metal level coupling capacitance.